Accuracy Comparisons

All Berkeley Design Automation Analog FastSPICE (AFS) accuracy comparisons are relative to the two industry leading “golden” simulators. The company guarantees identical accuracy to the SPICE noise floor when compared to these simulators’ results. That standard is built into the technology in that AFS solves the full circuit matrix, the original device equations, and takes no algorithmic shortcuts that could compromise accuracy. The simulator noise floor is the effective resolution based on a number of global SPICE settings most notably reltol, time-step control, and signal amplitude. Generally it is within ~0.1% of the magnitude of the desired signal.

All Berkeley Design Automation accuracy comparisons are based on running the same netlist and models in both simulators. AFS respects the same accuracy settings as the leading simulators (e.g., reltol, abstol, gmin, minstep, and maxstep). All comparisons start with both traditional SPICE and AFS using the same moderate or high (preferred) accuracy settings. Berkeley Design Automation sets its tools’ defaults more conservatively than the leading traditional SPICE simulators, so if there is a difference AFS is generally more accurate. Given subtle simulator algorithm differences in rare cases it is necessary to make minor adjustments to these settings to get equivalent results.

The designer – not Berkeley Design Automation – is always the standard for assessing accuracy. Designers typically compare accuracy using waveforms comparisons (e.g., overlays and measurements at specific nodes) or post processing (i.e., computations based on waveforms or measurements, e.g. to determine PLL jitter, power spectral density, etc.). In cases where these are not practical (e.g., traditional SPICE cannot produce results), designers use one or more of the following: comparison to silicon, other simulation methods (e.g., AMS or system-level numerical analysis), and engineering analysis.

Since AFS is inherently SPICE accurate, the company encourages designers to report any SPICE accuracy discrepancies above the simulator noise floor. The first step in debugging any discrepancy is to tighten the tolerances in both simulators. More often than not the traditional SPICE waveforms move toward the AFS waveforms which remain relatively stable through the tolerance-tightening process. This indicates that the AFS waveforms were indeed more accurate. As designers tighten tolerances for traditional SPICE, runtimes increase significantly and often the traditional SPICE simulator begins to fail to converge. This scenario is common, and designers are literally awestruck when it occurs. Of course AFS is not perfect. If a discrepancy remains even with very tight tolerances, Berkeley Design Automation isolates the cause and fixes any associated bug.

Performance Comparisons

All Analog FastSPICE performance comparisons are versus other simulators that have also produced nanometer SPICE accurate results. AFS achieves its performance advantage through computational efficiency that is fully effective for circuits with at least moderate complexity. AFS consistently delivers at least 5x performance versus traditional SPICE for circuits that are at least 1K elements and have >1-hour runtimes. The company does not focus on smaller circuits because traditional SPICE performance and capacity is sufficient for them. Despite their size, circuits with very high parasitic-to-transistor ratios can also be computationally simple. AFS consistently delivers at least 5x higher performance versus traditional SPICE for circuits where the ratio is 10 or less.

AFS comparisons use the same netlist with the same or equivalent accuracy settings as traditional SPICE. After running the netlist as is, Berkeley Design Automation removes any settings that the designer may have made to help the traditional SPICE simulator with convergence, accuracy, and performance (e.g., gmin, DC convergence method settings, abstol, reltol, and time-step control). AFS generally does not need this “help” and can produce accurate results within the SPICE noise floor with even higher performance without it.

All AFS performance comparisons are also based on equivalent hardware and operating system.

Capacity Comparisons

Berkeley Design Automation makes a distinction between load capacity and effective capacity – a distinction that is important for any simulator. Load capacity is a simulator’s required memory footprint for a given netlist. Analog FastSPICE creates a flat netlist like traditional SPICE. Its memory footprint is comparable and generally somewhat smaller than traditional SPICE. 

Effective capacity is a simulator’s true useful capacity. It is a function of achieving DC convergence and of transient performance. AFS has far superior DC convergence to traditional SPICE tools. Traditional SPICE tools can generally converge on netlists up to 100K elements or so, although there are many cases where they fail on substantially smaller circuits (e.g., those with complex device models). AFS routinely converges on circuits with >1M total elements and >250K transistors and has often gone much higher (e.g., >2M total elements and >1M transistors). Just as importantly, its superior performance enables AFS to complete large nanometer SPICE accurate simulations in a timeframe of relevance.

AFS does not use hierarchical partitioning. It is not intended to handle complete SoCs or large memories with tens-of-millions of elements such as those that digital fastSPICE tools can handle. Berkeley Design Automation uses the term “full-circuit” to refer to a top-level analog/RF circuit with perhaps limited transistor-level digital logic (such that it fits within the AFS effective capacity) – not a transistor-level representation of a large primarily digital design (e.g., an entire SoC or full memory IC).

Compatibility

Analog FastSPICE has true “plug-and-play” capability in the leading analog/RF circuit design flows. It utilizes industry-standard circuit simulator netlists without modification. Netlist compatibility is particularly challenging because there are an astronomical number of corner cases including those due to undocumented, ambiguously documented, and incorrectly documented “features.” Whenever practical, Berkeley Design Automation begins an evaluation by bringing a small number of circuit testcases in house to address any incompatibility issues. In most cases this process takes only a few days. Running through a few circuits for any given design group generally cleans up any and all compatibility issues for that group.

AFS supports industry-standard models without modification including BSIM 3, BSIM4, JFET, Gummel Poon, HICUM, VBIC, Mextram, BSIMSOI, Verilog A, b-sources, w-elements, s-parameters, and others. AFS is fully integrated into leading EDA design environment in which it is accessible via a pull-down menu option, uses the same forms, back-annotates to the schematic, etc. It also produces a number of common output formats including PSF (binary and ASCII), tr0, and FSDB for use with standard waveform tools.

For more information about how Precision Circuit Analysis tools compare with traditional SPICE and digital fastSPICE, see:

• Comparing Circuit Simulators
• Comparative Summary Scorecard