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Precision Circuit Analysis^TM Tools

Product Overview

	Analog FastSPICE
	Noise Analysis Option
	RF FastSPICE
	PLL Noise Analyzer

Technology Overview

	Comparing Simulators
	Evaluating Simulators
	Summary Scorecard

White Papers

Evaluation Request

Berkeley Design Automation Precision Circuit Analysis technology is the first major breakthrough in analog and RF verification technology in decades.

Traditional SPICE tools deliver SPICE accuracy, but are too slow and capacity-limited for big analog/RF verification tasks. Traditional “digital fastSPICE” simulators provide higher performance and capacity, but at the expense of accuracy that is critical to analog and RF verification. Berkeley Design Automation tools enable big analog/RF verification by uniquely delivering:

•   Identical waveforms as traditional SPICE down to the SPICE noise floor
•   5x-10x higher performance
•   5x-10x higher effective capacity
•   No block-level tuning (i.e., no need to tradeoff accuracy for speed)
•   No netlist, model, environment, or flow changes

The Precision Circuit Analysis tool line-up includes:

Analog FastSPICE^TM: circuit simulator delivers identical waveforms to traditional SPICE 5x-10x faster on 5x-10x larger circuits

Noise Analysis Option^TM: provides true SPICE accurate device noise analysis for all complex analog/RF blocks

RF FastSPICE^TM: multi-tone periodic analyzer delivers true SPICE accuracy without performance tradeoffs

PLL Noise Analyzer^TM: provides closed-loop integer-N noise analysis with ~1dB relative accuracy to silicon

Target Applications
Design teams from >50 companies have validated Precision Circuit Analysis technology’s accuracy, performance, and capacity on hundreds of production circuits. Many of these teams now use Berkeley Design Automation tools to solve big analog/RF verification problems that were previously impractical or impossible, including:

Complex-block characterization

Pre-layout simulation
Post-layout simulation
Variation analysis
Noise analysis
RF analysis

Full-circuit performance simulation

DC operating point analysis
Functional verification
Package and transmission-line effects
Targeted performance simulation

Specifications

Analog FastSPICE Analyses

DC (.op and sweep), AC, transient, .measure for DC and transient, noise, network analysis, pole-zero, transfer function, Monte Carlo, alter, and sweep
Co-simulation with leading Verilog® simulators

Supports standard “Spectre®-Verilog” use model
Works w/Cadence® NC-Verilog®, Cadence Verilog-XL, & Mentor® ModelSim®

Noise Analysis Option Analyses

Transient noise analysis
Time-domain periodic steady state (PSS, OSCPSS, VCOPSS), periodic small signal (PAC, PXF), periodic noise (PNOISE)
Oscillator phase noise analysis (OSCNOISE, VCONOIS) based on stochastic nonlinear engine

RF FastSPICE Analyses

Mixed-time/frequency envelope analysis

PLL Noise Analyzer Analyses

Full integer-N PLL noise and jitter analysis full noise sensitivity and contributor information

Flow Specifications

Netlist compatibility

HSPICE®
Spectre
VCD for simulation stimulus

Model support

BSIM3, BSIM4, BSIMSOI, MOS1
Gummel-Poon, Mextram
HICUM, VBIC, Juncap
Verilog-A, s-parameter, w-element

Outputs

PSF ASCII, PSF binary, tr0
Nutmeg ASCII, Nutbin, Nutbinf

Integration

Comprehensive Cadence Analog Design Environment (ADE) integration

Waveform viewer

WaveCrave™ waveform processor

Analog FastSPICE, Noise Analysis Option, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Synopsys and HSPICE are registered trademarks of Synopsys Inc. (NASDAQ:SNPS). Cadence, Spectre, NC-Verilog, and Verilog are registered trademarks of Cadence Design Systems Inc. (NASDAQ:CDNS). Mentor and ModelSim are registered trademarks of Mentor Graphics Corporation (NASDAQ: MENT). Any other trademarks or trade names mentioned are the property of their respective owners.