| |
|
|
|
« back to Press Releases main
Berkeley
Design Automation To Present Invited Paper at 2006 IEEE RFIC Symposium
SANTA CLARA, Calif.—June 12, 2006—Berkeley Design Automation, a
provider of innovative silicon analysis tools for analog/RF and
mixed-signal applications, today announced that a paper describing
powerful new analog/RF circuit analysis technology, authored by
co-founders Amit Narayan and Amit Mehrotra and CEO Ravi Subramanian,
will be presented at the 2006 IEEE RFIC Symposium in San Francisco,
Calif. on Tuesday, June 13.
The paper, entitled ‘Next-Generation Silicon Analysis Tools for RF
Integrated Circuits’, will be presented in the RFIC Simulation and
Layout Optimization session (Session RTU1C). The session starts at 8AM
on Tuesday, June 13.
Dr. Narayan and Dr. Mehrotra founded Berkeley Design Automation in
2003. Both received their B.Tech. in Electrical Engineering from Indian
Institute of Technology at Kanpur and did their doctoral research
together at the University of California at Berkeley. Dr. Subramanian
received his BSEE from the California Institute of Technology and
earned his Ph.D. in EECS from the University of California at Berkeley,
where he was a recipient of the prestigious UC Regent's Fellowship.
The 2006 IEEE Radio Frequency Integrated Circuits Symposium (RFIC-2006)
will be held at the Moscone Center in San Francisco, California on June
11-13, 2006. For further information, visit: http://www.rfic2006.org.
About Berkeley Design Automation
Berkeley Design Automation Inc. was founded in 2003 to address the
verification challenges in the design of next-generation
high-performance analog/RF integrated circuits (ICs). Berkeley Design
Automation is a venture-backed, private company funded by Woodside Fund
and Bessemer Venture Partners. The company’s technology characterizes
the nonlinear, time-varying behavior of complex analog and RF circuits,
providing extremely accurate predictions that dramatically reduce the
need for silicon re-spins. The company’s first product, PLL Noise
Analyzer(™), the industry's first noise analysis tool for phase-locked
loops (PLLs), has already been adopted by semiconductor industry
leaders. For more information, see http://www.berkeley-da.com.
PLL Noise Analyzer, Stochastic
Nonlinear Engine, and Precision Circuit Analysis are trademarks of
Berkeley Design Automation, Inc.
Berkeley Design is a registered trademark of Berkeley Design
Automation, Inc.
HSPICE is a registered trademark of Synopsys Inc. (NASDAQ:SNPS).
Spectre is a registered trademark of Cadence Design Systems Inc.
(NASDAQ:CDNS).
Berkeley Design Automation
Tom Ferry, 408-496-6600, x225, thomas.ferry@berkeley-da.com.
PR for Berkeley Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com.
|
|
|
