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P.A. Semi Successfully
Develops 65nm, 2.5 GHz PLLs For PWRficientTM
Processor Using Berkeley Design Automation’s Noise Analyzer
PLL Noise
AnalyzerTM’s
Fast and Silicon-Accurate Analysis Enables Processor Start-Up To Meet
Stringent Jitter and Power Specifications
SANTA CLARA, Calif. —[January 9, 2006] —
Berkeley Design Automation Inc., a provider of innovative silicon
analysis tools for analog/RF and mixed-signal applications, today
announced that P.A. Semi, a Silicon Valley startup developing the
high-performance, low-power PWRficient™ processor family, has
successfully deployed PLL Noise Analyzer on its 65nm processor chip.
P.A. Semi was able to meet extremely demanding noise and jitter
specifications on the processor’s PLLs, that run up to 2.5GHz, while
optimizing for power and area using Berkeley Design’s advanced circuit
analysis technology.
“At P.A. Semi, we are designing high performance, power-efficient,
multi-core processors that offer up to a ten-fold increase in
performance per watt,” said Sribalan Santhanam, vice president of
engineering, Design Group, at P.A. Semi. “Our applications demand
ultra-low noise and jitter for clocking and I/O, and Berkeley Design
Automation’s PLL Noise Analyzer enabled us to quickly and accurately
analyze the noise and jitter of our 65nm PLLs.”
“Noise analysis of circuits at 65nm is very complex,” said Vincent von
Kaenel, Director of Analog Engineering, P.A. Semi. “PLLs pose one of
the biggest challenges due to the highly nonlinear nature of the
circuit, coupled with the variability of the process. PLL Noise
Analyzer enabled us to accurately analyze PLL noise and jitter and
characterize the top noise contributors quickly before we taped out our
65nm PLLs. We successfully met our noise and jitter targets.”
Berkeley Design Automation’s PLL Noise Analyzer is based on
next-generation circuit analysis technologies that allow designers to
accurately characterize the noise and jitter performance of their
designs before tape-out. Berkeley Design’s proprietary Stochastic
Nonlinear EngineTM
is the foundation of PLL Noise Analyzer and it provides unprecedented
analysis speed and accuracy. With the fast and accurate noise analysis
provided by PLL Noise Analyzer, designers are free to confidently
optimize their PLLs for area and power.
‘We are very pleased that Berkeley Design’s accurate noise analysis
technology has enabled P.A. Semi to meet their very aggressive noise
and power targets in their first tape-out,” said Ravi Subramanian,
President and CEO of Berkeley Design Automation. “Our advanced silicon
analysis technology was designed to address exactly these types of
challenges. By providing speed and accuracy in these new analyses, we
can accelerate the time-to-volume production of complex designs such as
PA Semi’s PWRficient processor.”
About Berkeley
Design Automation
Berkeley Design Automation Inc. was founded in 2003 to address the
verification challenges in the design of next-generation
high-performance analog/RF integrated circuits (ICs). Berkeley Design
Automation is a venture-backed, private company funded by Woodside Fund
and Bessemer Venture Partners. The company’s technology characterizes
the nonlinear, time-varying behavior of complex analog and RF circuits,
providing extremely accurate predictions that dramatically reduce the
need for silicon re-spins. The company’s first product, PLL Noise
Analyzer, the industry's only noise analysis tool for phase-locked
loops (PLLs), has been adopted by semiconductor industry leaders. For
more information, see http://www.berkeley-da.com.
About PLL
Noise Analyzer
PLL Noise Analyzer fits easily into existing analog/RF verification
flows. It reads HSPICE and Spectre format netlists and standard device
models. PLL Noise Analyzer is available for Sun and Linux operating
systems.
PLL Noise Analyzer and Stochastic
Nonlinear Engine are trademarks of Berkeley Design Automation, Inc.
Berkeley Design is a registered trademark of Berkeley Design
Automation, Inc.
PWRficient is a trademark of P.A. Semi Inc.
HSPICE is a registered trademark of Synopsys Inc. Spectre is a
registered trademark of Cadence Design Systems Inc.
Editorial
Contact:
PR for Berkeley Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com
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