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Introducing Berkeley Design
Automation - Delivering Next-Generation Analog/RF IC Verification
Technology
Company's breakthrough technology dramatically improves verification
accuracy of high-performance analog/RF integrated circuits.
SANTA CLARA, Calif. - May 23, 2005 -
Berkeley Design Automation Inc., a new electronic design automation
company founded in 2003, today launched its entry into the analog/RF
integrated circuit (IC) verification market. The company's mission is
to address the major verification challenges in the design of
high-performance analog/RF ICs. The company’s technology, based on
research conducted by the founders at the University of California at
Berkeley and the University of Illinois, is uniquely able to
characterize the nonlinear, stochastic, time-varying behavior of
complex analog and RF circuits. Products using this technology provide
very accurate predictions that dramatically reduce the need for silicon
respins.
The company also announced its initial
product, PLL Noise Analyzer™, the industry's first noise analysis tool
for circuits containing phase-locked loops (PLLs) (see today’s related
press release). The tool has already been adopted by leading
semiconductor companies and is proven to dramatically improve their
ability to accurately analyze noise before tape-out and to reduce
silicon respins.
Berkeley Design Automation was founded by
Amit Narayan, vice president of engineering; and Amit Mehrotra, chief
technology officer; who did their doctoral research together at the
University of California at Berkeley. Amit Mehrotra’s Ph.D. thesis
topic and his research at the University of Illinois set the foundation
for Berkeley Design Automation’s breakthrough stochastic nonlinear
circuit analysis technology. This technology enables the accurate
modeling of the nonlinear, time-varying behavior of circuits at the
transistor level.
"Analog circuits are pervasive today, even
in the most 'digital' of designs", said Dr. Ravi Subramanian, Berkeley
Design Automation's president and CEO. "Our customers have told us that
the greatest challenge in the design process today is to reduce the
rate of silicon spins required to achieve volume production for these
analog-rich ICs. Berkeley Design Automation has successfully delivered
to the market a new generation of IC verification technology that has
been customer-validated to provide greater predictability and certainty
to the design of these complex ICs."
Dealing with the nonlinear and stochastic
behavior in analog circuits is a major challenge for designers because
the analog circuits not only generate noise internally, but they are
also extremely sensitive to noise generated by other circuits in an
SoC. Existing analog verification tools lack the circuit analysis
technology required to accurately analyze noise when operating in a
nonlinear time-varying environment. Often, designers are forced to use
silicon iterations and a variety of approximation methods to analyze
noise in order to minimize noise problems.
“Noise and nonlinearity are becoming the
limiting factors in the design of high performance analog and mixed
signal circuits,” said Abbas El Gamal, Professor of Electrical
Engineering and Director of the Information Systems Lab at Stanford
University. “The increased performance demands and circuit complexities
make the noise analysis approaches used in traditional tools grossly
inaccurate. The circuit analysis technology developed by Berkeley
Design Automation provides fast and accurate noise analysis for current
and future analog/RF circuits.”
“Noise analysis of nonlinear circuits has
been a difficult problem for a very long time,” said Floyd Gardner,
IEEE Fellow, a leading international authority on phase-locked loops,
and a member of Berkeley Design Automation’s Technical Advisory Board.
“This difficulty has made the design of many of today’s analog-rich
circuits such as PLLs and clock data recovery a time-consuming,
error-prone, and expensive process, often requiring multiple silicon
iterations. Berkeley Design Automation has demonstrated that it can
provide designers a significant breakthrough in how they analyze these
circuits, enabling them to accurately characterize their designs before
silicon tape-out.”
The ability to reliably deliver working
silicon on time is a key competitive advantage to semiconductor
companies. “We view NEC’s ability to reliably deliver high-quality
analog IP as a competitive advantage for us in the European market,”
said Matthias Voigt, General Manager, NEC Electronics GmbH. “Using PLL
Noise Analyzer, NEC is able to accurately analyze full PLL noise before
tape-out. This capability helps NEC deliver working silicon on time.”
“Our mission is to bring to market solutions
to address some of the toughest problems related to design and
verification of high complexity analog and RF integrated circuits,”
said Dr. Narayan. “We are very pleased that our Stochastic Nonlinear
Engine(™) has already been successfully used on more than 35 customer
designs, in technologies from 0.25 micron to sub-90 nanometers, and has
been adopted by leading semiconductor companies as a critical part of
their verification flow.”
At the 42nd Design Automation Conference in
Anaheim, CA in June 2005, Berkeley Design Automation will conduct
product demonstrations and describe this revolutionary technology to
customers. Demo registration is available at http://www.berkeley-da.com.
About Berkeley Design
Automation
Berkeley Design Automation Inc. was founded in 2003 to address the
verification needs of high-performance analog/RF integrated circuits
(ICs). Berkeley Design Automation is a venture-backed, private company
funded by Woodside Fund and Bessemer Venture Partners. The company’s
technology characterizes the nonlinear, time-varying behavior of
complex analog and RF circuits, providing extremely accurate
predictions that dramatically reduce the need for silicon respins. The
company’s first product, PLL Noise Analyzer™, the industry's first
noise analysis tool for phase-locked loops (PLLs), has already been
adopted by semiconductor industry leaders. For more information, see
www.berkeley-da.com.
# # #
PLL Noise Analyzer and
Stochastic Nonlinear Engine are trademarks of Berkeley Design
Automation Inc.
Editorial Contact:
PR for Berkeley Design Automation – Cayenne Communication LLC
Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com
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