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Full-Circuit Performance Simulation
targets
top-level analog/RF circuits reaching >2M total elements
including
>1M transistors. Verification tasks include DC operating point
analysis, functional verification, package and transmission-line
analysis, and targeted performance simulations.
Targeted full-circuit performance simulation represents the ultimate
challenge
in Big Analog/RF Verification, and it illustrates the truly
revolutionary results that are possible with Berkeley Design Automation
technology.
True SPICE accuracy and full-circuit capacity are prerequisites for
running performance simulation. With “only” 5x-10x
performance over
traditional SPICE, it is not practical to run extensive system-level
behavior (e.g., realistic communications traffic through a
transceiver). However, it is possible for the first time to create and
run targeted performance simulations to verify known circuit worry
cases such as key specifications (power, frequencies, noise, SNR) under
extreme conditions. This ability gives design teams a powerful window
into their silicon performance weeks and hundreds-of-thousands of
dollars sooner than would be possible otherwise. Table 9 contains five
full-circuit targeted performance simulations using AFS.
Full-Circuit
Targeted Performance Simulation Examples
In the first two examples traditional SPICE could not converge, so the
design teams tried digital fastSPICE only to give up due to obvious
inaccuracies. In just 12 hours Analog
FastSPICE (AFS) completed
transient analysis for the top-level microcontroller analog circuitry.
This had proven impossible with all other simulators. In the second
case, the designer ran digital fastSPICE to get full-circuit power
numbers for a low-power GPS receiver. When he changed the digital
fastSPICE block-level simulator tuning slightly, the simulator produced
results 3 orders of magnitude greater for the same netlist. The results
literally changed from milliamps to amps. Needless to say, the designer
thereafter did not trust digital fastSPICE. AFS delivered results that
were within 20% of the designer’s hand calculation and the
results
varied as expected across a variety of runs.
In the last three examples the design teams decided not to even try
digital fastSPICE because of its insufficient accuracy. Traditional
SPICE was able to converge on the PMA receiver, but the runtime was so
long that the designer stopped the run which he estimated would have
required over 19 days to complete. AFS completed the run and delivered
true SPICE accurate results in less than 3 days. AFS was even faster
compared to traditional SPICE in the DDR3 SRAM example. Traditional
SPICE required extensive initial conditions to converge on the
>500K
total elements and >100K transistors circuit. It completed the
run
in 4.7 days. AFS was able to converge without the initial conditions
and complete the run in only 14 hours. The last example is a receiver
with CDR and adaptive equalizer. It too was >500K total elements
and
>100K transistors. AFS produced results that were otherwise
impossible to obtain prior to measuring actual silicon.
Click here to continue to return to Big
Analog/RF Verification.
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