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Full-Circuit Performance Simulation
targets
top-level analog/RF circuits reaching >2M total elements
including
>1M transistors. Verification tasks include DC operating point
analysis, functional verification, package and transmission-line
analysis, and targeted performance simulations.
After spending months working on detailed circuit-level verification,
one of the most frustrating experiences a design team can face is
silicon that does not deliver to specification due to package or
transmission-line effects. Unable to adequately analyze these effects,
designers must either consciously over-design or live with increasingly
significant risks. Traditional SPICE runtime and capacity limitations
make it impractical for this application in many cases, and digital
fastSPICE simulators cannot produce the required accuracy and does not
have adequate inductor and transmission-line support.
Berkeley Design Automation categorizes this analysis as full-circuit
because it is often desirable to run it at that point in the design
flow. However, it is also possible to isolate the analysis to just
those complex blocks that interface with the package inductors or
transmission lines, as is the case examples 2-4 in the table below.
Full-Circuit
Package and Transmission-Line Analysis Examples
The first example illustrates the wall that many design teams will hit
soon, if they have not done so already. It is a memory in package. The
memory is 244K elements, almost all of which are transistors. The
package model contains 42 inductors and 145 mutual inductors. The
company producing this memory IC unexpectedly encountered a significant
yield loss when they moved from 90nm to 65nm. A designer traced the
problem to package inductance. They had historically relied on digital
fastSPICE for this analysis because their traditional SPICE simulator
could not converge on such a large circuit. However, digital fastSPICE
results badly mislead them at 65nm. They were able to run Analog
FastSPICE and get true SPICE accuracy with just a 24-hour
run.
AFS ran the 3GHz SerDes example 6.5x faster, and in the third example
AFS ran the distributed VCO 10x faster. The video coax cable equalizer
example includes 1800 total inductors, 5 package inductors, and a
transmission line. Digital fastSPICE was not even an option. AFS
completed this analysis 5x faster than traditional SPICE.
Click here to continue to Full Circuit: Targeted
Performance
Simulation.
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