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Full-Circuit Performance Simulation
targets
top-level analog/RF circuits reaching >2M total elements
including
>1M transistors. Verification tasks include DC operating point
analysis, functional verification, package and transmission-line
analysis, and targeted performance simulations.
Design teams use digital fastSPICE or mixed-mode simulation for
full-circuit functional verification in order to check connectivity and
overall behavior under a variety of conditions including different
configurations, different operating modes, during power-up and during
reset. As pointed out above, neither digital fastSPICE nor mixed-mode
simulation has adequate accuracy to check connectivity thoroughly
(e.g., they cannot check low-order bit connectivity in datapaths).
Simulation accuracy is important even when verifying only functional
behavior. Since small inaccuracies can lead to a qualitatively
different result, it is critical that design teams be aware of the
risks of false positives and false negatives. Getting “good
enough”
simulation with digital fastSPICE entails a process of tuning the
simulator to each circuit block until the simulator produces the
expected behavior. The process is to some extent self-referential (and
therefore not an independent verification) in that in order to check
expected behavior, the designer must tune the simulator to try to get
it to produce the behavior the user expects. Using a mixed-mode
simulator for functional verification has a similar limitation with
respect to having to tune the circuit’s behavioral models to
ensure
they are accurate enough.
Analog
FastSPICE (AFS) is always true SPICE accurate, so every
simulation is a full performance simulation – not a
functional-only
simulation. The examples in the table below are labeled functional
verification because the design team was already running or trying to
run functional verification rather than a full performance simulation.
In each case the design team tried to run traditional SPICE first
because doing so would eliminate block-level simulator tuning and
ensure the functional behavior was correct. In the first three examples
traditional SPICE would not converge. In the last example, it converged
but it was so slow that the design team changed approaches.
Full-Circuit
Functional
Verification Examples
The first example was a 65nm SRAM embedded in a microprocessor. The
designer had already tuned a digital fastSPICE simulator and obtained a
3.3 hr runtime, but he was concerned about very subtle behavior during
reset which is impossible to check with the limited digital fastSPICE
accuracy. His first run with AFS was 1.2 hours – 2.5x faster
without
any simulator tuning. More importantly, the AFS results were true SPICE
accurate enabling the designer to accurately measure subtle behavior
during reset. The full circuit in this case was more than 1M total
elements.
In the PCI receiver example, digital fastSPICE was 14 hours versus 24
hours for AFS. AFS was within 2x without requiring any block-level
simulator tuning and delivering true SPICE accurate results. Without
the AFS run, the design team could never be sure if their digital
fastSPICE run was producing “good enough” results
or a false positive.
The next example is 5 PLLs with a regulator. In this case the designer
could only get digital fastSPICE to produce what the designer reported
as “bizarre.” AFS converged and completed the
transient run for the
nearly 400K transistor circuit in 14 days. The results were accurate to
the SPICE noise floor.
The next example in the table above is an I2C circuit that included a
bandgap, VCO, and charge pump. At only 52K total elements, it was small
enough for traditional SPICE to converge, but the designers aborted the
transient run after a few days because they estimated it would take 40
days to complete. This type of projected runtime is far more common
than some may think or wish to admit. When design teams hit this type
of problem, they generally change approaches or decide the verification
task is infeasible. In this case the design team adopted a traditional
SPICE-HDL co-simulation approach. While doing so sacrificed some
accuracy at the analog-digital interface, it got the runtime down to a
reasonable 4 days. AFS ran the full-transistor level version of the
circuit in the same 4 days while providing the design team the accuracy
they originally required.
In addition to full-circuit functional verification, design teams may
also run full-chip functional verification that includes all of the
digital logic and analog/RF circuitry. Generally they choose digital
fastSPICE, mixed-mode, or traditional SPICE-HDL co-simulation. There
are advantages and disadvantages to each approach. Traditional
SPICE-HDL co-simulation is perhaps the most natural choice because it
leaves the circuitry at the transistor level and the logic at the HDL
level. Unfortunately traditional SPICE simulator performance and
capacity limitations have made it impractical in many cases. Although
AFS does not currently have this capability, adding it would enable a
new class of Big Analog/RF Verification.
Click here to continue to Full Circuit: Package
and
Transmission-Line Analysis.
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