Full-Circuit Performance Simulation targets top-level analog/RF circuits reaching >2M total elements including >1M transistors. Verification tasks include DC operating point analysis, functional verification, package and transmission-line analysis, and targeted performance simulations.

Berkeley Design Automation uses the term “full-circuit” to represent the top-level analog/RF circuitry and nominal integrated transistor-level digital logic – not a transistor-level predominantly digital design (e.g., entire SoC with SerDes). Most analog/RF design teams learned long ago that full-circuit performance simulation is impossible or at least completely infeasible within a reasonable timeframe.

With today’s top-level analog/RF circuits often surpassing 1M total elements including >250K transistors, the days when traditional SPICE could perform meaningful analysis are long past. This leaves circuit designers with the dilemma of using tools that do not have SPICE-accurate resolution – digital fastSPICE and/or mixed-mode simulation (e.g., AMS simulators) – to verify the final transistor-level implementation. This is a like trying to use a standard ruler to measure to a thousandth of an inch. At best it is possible to identify gross errors and even that might require significant judgment. Prior to Berkeley Design Automation, the only way designers could see accurate pin-to-pin full-circuit performance was to tapeout and measure the resulting silicon.

As an example of the current limitations of full-circuit verification, consider analog/RF full circuits that include ADCs. Many design teams use digital fastSPICE or mixed-mode simulator functional verification to check their ADCs connectivity in the top-level implementation. Getting to even 1% accuracy is very difficult using either type of simulation, and without a golden reference one can never tell if they are even that close. Assuming accuracy to within 1%, it is possible to verify only the ADC’s most significant 6 bits. That is hardly sufficient for today’s ADCs that are routinely 12 bits or more. Although it may not be obvious, all remaining bit connections are literally unverifiable with these simulators. The only way the design team will know about any lower-order bit disconnects or misconnects is when the silicon does not meet specifications. A true SPICE accurate simulator would catch such problems with DC operating point analysis many weeks and hundreds-of-thousands of dollars sooner.

Analyzing the DC operating point (i.e., a set of currents and voltages for every node that satisfy Kirchhoff’s Laws for a given initial DC condition) is the simplest way to do basic circuit connectivity checks. DC operating points are also very valuable for checking basic current and voltage assumptions, determining static power consumption, and running electromigration analysis.

Full-Circuit DC Operating Point Analysis Examples