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Complex-Block Characterization
includes
computationally intensive verification tasks from pre- and post-layout
simulation to variation, noise, and RF analysis on circuits such as
PLLs, DLLs, ADCs, SerDes, Tx chains, Rx chains, and memory interfaces.
Noise has a dramatic effect on system-level performance, e.g.,
signal-to-noise ratio (SNR) and bit-error rate (BER). Designers of
low-voltage, high-frequency circuits ignore noise at their own risk.
That risk goes up significantly with circuits that have noise sensitive
architectures, tight specifications, and are implemented on bulk CMOS
processes. Most common complex blocks are highly susceptible to noise,
including sigma-delta ADCs, fractional-N PLLs, integer-N PLLs, and
high-speed I/Os.
Noise analysis should include random (thermal and flicker) and
deterministic noise sources. There are three primary transistor-level
noise analysis techniques:
- Transient
Noise Analysis: injects noise for each node at each
time-step
during transient simulation to produce output waveforms that include
the effects of realistic noise. Designers post-process the noisy
waveforms to determine the noise effect. This technique is valid for
all types of circuits and is the only transistor-level noise analysis
technique for non-periodic circuits such as sigma-delta ADCs and frac-N
PLLs. Some traditional SPICE simulators offer transient noise analysis;
however it is so notoriously slow that it is infeasible in most cases.
- Periodic
Noise Analysis (pnoise): directly analyzes noise in
periodic
driven circuits such as dividers, switch cap filters, and phase
detectors. Pnoise analysis is faster than transient noise analysis for
this type of circuit and provides additional diagnostic information
(e.g., individual noise source contributions). Traditional RF
simulators (Shooting-Newton and harmonic balance) have periodic steady
state (PSS) convergence problems for complex periodic circuits and
inherently tradeoff accuracy, performance, and capacity.
- Oscillator
Noise Analysis (oscnoise/vconoise): directly analyzes
noise in
periodic autonomous circuits such as VCOs (LC-tank and ring oscillator)
and crystal oscillators. Oscnoise/vconoise analysis is faster than
transient noise analysis for this type of circuit and provides
additional diagnostic information (e.g., individual noise source
contributions). Traditional RF simulators have periodic-steady-state
convergence problems for complex periodic circuits; make inherent
approximations that adversely effect accuracy; and inherently tradeoff
accuracy, performance, and capacity.
A simple methodology analyzing noise in complex blocks starts with the
component sub-circuits. The first step is to apply periodic noise and
oscillator noise to sub-circuits within a complex block wherever
applicable because these techniques are faster and provide superior
diagnostics to transient noise. In parallel, apply transient noise to
all other sub-circuits. Finally, use transient noise to analyze noise
on the entire complex block.
Due to limitations in traditional SPICE
and RF tools, very few design teams perform transistor-level noise
analysis at the complex-block level and many designers need to simplify
even more complex sub-circuits (e.g., VCO with buffer, bias, and
divider) in order to perform noise analysis. Digital fastSPICE tools do
not offer noise analysis capabilities; given their level of inaccuracy,
transient noise analysis would be meaningless, and digital fastSPICE
tools do not have the technical foundation for periodic or oscillator
noise analysis.
Complex-Block Noise Analysis Examples
Berkeley Design Automation provides comprehensive, world-class noise
analysis with characteristics that parallel those for its transient
simulation, i.e., full accuracy, 5x-10x faster, and with 5x-10x higher
effective capacity for complex blocks and complex sub-circuits within
them. These capabilities make it practical for the first time to
thoroughly characterize noise in sensitive complex blocks including
sigma-delta ADCs, fractional-N PLLs, and SerDes/CDRs. The company also
offers the industry’s only non-approximate closed-loop
analysis tool
for integer-N PLLs – PLL Noise Analyzer™ (PNA)
which utilizes the
company’s transient, pnoise, oscnoise/vconoise engines along
with its
proprietary Stochastic Nonlinear Engine™ for the full PLL.
More than 10
leading semiconductor companies have verified this tool’s
accuracy to
within 1 dB relative accuracy (2-3 dB absolute accuracy) to silicon
thus proving the accuracy of the underlying engines.
The table above contains Berkeley Design Automation noise analysis
results on a range of production testcases. The first example is a
simple jitter analysis using transient simulation only (not transient
noise analysis). This leading “golden” accurate
traditional SPICE had a
simulator-induced noise floor that was so high that the signal was
difficult to discern and the jitter numbers were unusable. The designer
was able to lower the noise floor by tightening time-steps, but this
resulted in unacceptably long simulations. Analog FastSPICE
(AFS) ran
the circuit with acceptable accuracy, providing a sharp signal waveform
and 7.4x faster than traditional SPICE (which produced unacceptable
results). This PLL jitter analysis illustrates the increasing need for
even more accuracy than traditional SPICE defaults.
The next two examples are transient noise analyses on sigma-delta ADCs.
AFS with transient noise analysis was 10x faster in the first example.
In the second example, the designer did not run transient noise
analysis on traditional SPICE because transient simulation alone took
more than 4.5 days. AFS completed transient noise 4.5x faster than the
traditional SPICE transient only simulation on this circuit. The dual
receiver and VCO with buffer, bias, and divider are examples of
circuits where traditional RF simulation could not converge which made
phase noise and oscillator noise respectively impossible. RF FastSPICE
completed each in <1 hour. The last example illustrates the
company’s unique PLL noise analysis technology.
Click here to continue to Complex Block: RF
Periodic Analysis.
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