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Complex-Block Characterization
includes
computationally intensive verification tasks from pre- and post-layout
simulation to variation, noise, and RF analysis on circuits such as
PLLs, DLLs, ADCs, SerDes, Tx chains, Rx chains, and memory interfaces.
In today’s complex blocks, designers disregard parasitics at
their
risk. During pre-layout simulation designers include the most critical
parasitics only, i.e., those they expect to have first-order functional
and performance effects. Designers run post-layout transient simulation
to see second-order performance effects, as well as to verify their
choices for critical first-order parasitics in the pre-layout
simulation.
Post-layout netlists generally have on the order of 4x-10x more total
elements than the equivalent pre-layout netlist, although the number
can sometimes be much higher. Resistors and capacitors dominate the
total count, but parasitics increasingly include inductance and even
mutual inductance. Even though resistors and capacitors are simple
components, the total element count often increases beyond 100K
elements. In many cases traditional SPICE simulators simply cannot
converge on such circuits. When traditional SPICE does converge, the
runtimes can be 2x-4x or longer versus the circuit’s
pre-layout
simulation.
Digital fastSPICE simulators generally do not even have
sufficient accuracy for pre-layout simulation. Even designers who use
digital fastSPICE for pre-layout generally consider applying them post
layout is a waste of time because their results will be misleading at
best. This is often a moot point because of digital
fastSPICE’s
notoriously poor support of inductors.
Complex-Block
Post-Layout Transient Examples
The first circuit in the table above exemplifies the problems with
traditional SPICE and digital fastSPICE for post-layout complex blocks.
It is a 3rd-order sigma-delta ADC with ~14x more parasitics than
transistors. SPICE did not converge (DNC), so the designer tried
digital fastSPICE. After block-level tuning the designer got digital
fastSPICE to complete a run in 333 hours – that’s
about 1.5 weeks and
18x longer than the pre-layout SPICE run. Fortunately in this case the
designer was evaluating the simulator on a circuit that was already in
silicon. The digital fastSPICE SNR was off by 5 dB. Not surprisingly
the designer deemed the accuracy unacceptable and decided not to use
digital fastSPICE for such applications in the future. The designer
tried Analog FastSPICE
(AFS)
on the exact same netlist and was
astounded that the tool completed transient in just 29 hours with
results within 1 dB of silicon.
The other examples also clearly demonstrate how AFS easily handles
otherwise impractical or impossible problems. The DLL has over 200K
total elements; AFS reduced the runtime from 1.8 days to 7.3 hours. Few
design teams have 3.4 weeks to run the post-layout PLL, but most would
be willing to spend the 3.2 day AFS runtime to check it. The next
example is a second sigma-delta ADC in which AFS was 25x faster.
The last three circuits have especially high parasitic-to-transistor
ratios. The video ADC is the post-layout version of the pre-layout
video ADC in the Complex Block: Pre-layout
simulation page. There were 842K total elements and 11.3K
transistors in the post-layout netlist for a ~75x ratio. Traditional
SPICE was able to converge and complete transient analysis in 8.6 days.
AFS took only 16 hours. This 13x speedup is comparable to the 15x
speedup pre-layout. The bias circuit had a 100x ratio, did not converge
in SPICE, and finished in just 48 minutes using AFS. The last circuit,
a VCO, included inductors and mutual inductors in addition to resistors
and capacitors and had an overall parasitic-to-transistor ratio over
45x. The designer’s “golden” SPICE
simulator took 22x longer than AFS
to produce the same results.
Click here to continue to Complex Block: Variation
Analysis.
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