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Complex-Block Characterization
includes
computationally intensive verification tasks from pre- and post-layout
simulation to variation, noise, and RF analysis on circuits such as
PLLs, DLLs, ADCs, SerDes, Tx chains, Rx chains, and memory interfaces.
Of these tasks, pre-layout transient simulation is by far the simplest,
least time consuming, and least demanding in terms of simulator
accuracy (i.e., a low noise floor). Yet designers are struggling to
complete enough pre-layout transient simulation for complex blocks with
their current tools.
Consider phase-locked loops, for example. PLLs have notoriously long
transient runtimes, in part due to the widely disparate frequencies
which can range many orders-of-magnitude (e.g., kHz to GHz). Designers
need to verify that PLLs lock correctly and check key metrics such as
control voltage, charge-pump current, frequency, and output jitter.
Pre-layout transient runtimes for high-frequency, nanometer PLLs
generally range from multiple days to over a week using traditional
SPICE.
PLLs’ characteristics make them a favorite for designers to
try using
digital fastSPICE. The reasoning is: 1) digital fastSPICE can take
advantage of PLL sub-circuits’ widely different frequencies
through
block-level tuning to reduce simulation time, and 2) digital fastSPICE
provides “good enough” accuracy because locking
simulations are
primarily functional. Designers know that using digital fastSPICE
requires hours or even days of tuning and they know that not having
true SPICE accuracy introduces risk, but many figure that these
downsides are worthwhile when the only option is extremely long
traditional SPICE runs that introduce known schedule risk.
Perhaps because PLLs have been a favorite analog application for
digital fastSPICE, they are also a common example of failed silicon.
The first time a PLL designer sees functionally inaccurate behavior
from a digital fastSPICE simulator (i.e., a PLL seems to lock when the
circuit actually won’t lock or vice versa), they generally
never again
believe digital fastSPICE accuracy is “good
enough.” Lucky design teams
catch these problems by checking a suspicious result with traditional
SPICE. The unfortunate ones see the real PLL behavior for the first
time in silicon.
Sigma-delta ADCs, which also contain frequencies that can range
orders-of-magnitude, are an example of circuits at the other extreme in
that they often require accuracy that is tighter than the traditional
SPICE defaults deliver. Designers must tighten tolerances and
time-steps, which considerably slows traditional SPICE and sometimes
causes it to stop converging. Digital fastSPICE tools have no place
here.
Other complex blocks have transient accuracy requirements somewhere
between PLL locking simulation and sigma-delta ADC transient analysis.
Most have runtimes that are many hours to many days long. Even those at
the shorter end of this spectrum can be problematic when they require
many iterations; 4-hour runtimes mean designers get only 3 iterations
per day (one based on overnight runs and 2 based on daytime runs).
Complex-Block
Pre-Layout Transient Examples
The table above shows a number of examples with traditional SPICE
runtimes versus Berkeley Design Automation Analog FastSPICE(AFS)
circuit simulation runtimes. All comparisons are with one of the
industry’s two leading “golden” SPICE
simulators. All examples utilize
the original netlist and the designer verified the AFS waveforms
matched traditional SPICE down to the SPICE noise floor (generally 0.1%
or tighter with reltol = 1E-4 or less). All performance numbers are
based on equivalent hardware.
Berkeley Design Automation consistently delivers at least 5x higher
performance with identical or better accuracy for circuits with
>1K
elements and >1 hr runtimes. The impact of doing so on these
circuits is dramatic. In the first PLL example, AFS turned 3 weeks into
less than 1 day, and by doing so turned an impractical verification
task into one that is quite manageable. This is admittedly a rather
extreme example. The next example is a more typical PLL where AFS
delivered 14x, slashing over 3 days to less than 5.5 hours. The next
three examples are ADCs. AFS took the 4-day sigma-delta ADC run from
over 4 days to about a 1/2 day, the pipelined ADC from overnight to 3.2
hours, and the video ADC from 7 hours to 25 minutes.
DC converters are another class of circuits that require long transient
simulations with true SPICE accuracy. Even though it is only 12.5K
total elements, the multi-channel DC:DC did not converge in traditional
SPICE. AFS converged and finished the required transient simulation in
a little over 3 days. The power IC DC converter is much larger with
33.4K transistors. Traditional SPICE did converge on this circuit, but
it took nearly 1 week to simulate what AFS completed in less than 1 day
– with identical accuracy.
The remaining circuits are a receive chain, frequency synthesizer, and
automatic gain control circuit with bandgap and bias. AFS completed
these pre-layout simulations 5x, 9x, and 36x faster, respectively, than
the design teams’ traditional SPICE simulator. It bears
repeating that
in all cases in this paper, AFS delivered these performance numbers
while delivering waveforms that the designer verified were at least as
accurate as their “golden” traditional SPICE
simulator.
As would be expected, designers for most these circuits were skeptical
prior to running AFS. After running the tool themselves and verifying
the accuracy of the results, many were literally astonished. They
firmly believed that the only way to get higher performance was to
compromise accuracy. They believed that the company was either
exaggerating its claims or not fully disclosing some tool limitation.
Once designers experience AFS accuracy and performance firsthand, they
immediately try it on even more challenging problems. With complex
blocks, that means more detailed characterization, generally starting
with post-layout transient simulation.
Click here to continue to Complex Block: Post-Layout
Simulation.
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