Clock circuits including phase locked loops (PLLs) and delay-locked loops (DLLs) are the timing heart of nearly all integrated circuits - from large system-on-a-chip (SoC) devices to wireless transceivers. PLL and DLL circuits implemented in nanometer CMOS technologies must reliably produce GHz-speed clock outputs with very low noise and jitter and conform to tight power consumption constraints. PLL and DLL designers must verify that the circuit locks onto the desired frequency in the required time, meets jitter, duty cycle, and power requirements for a wide variety of functional modes across all operating conditions and process, voltage, temperature corners. The result is many long transient simulations that require full SPICE accuracy.
                           
The widely separated frequencies present in PLLs and DLLs pose a difficult challenge for traditional SPICE simulators. For example, a PLL might produce an output clock signal with a frequency in the GHz range and also have a loop bandwidth in the kHz range. This forces designers to simulate with picosecond time steps to capture the GHz signal and also run the simulation long enough to capture the kHz signal behavior. Traditional SPICE simulators employ single-rate transient engines which are extremely inefficient for such tasks.

Analog FastSPICE incorporates the industry’s first and only multi-rate transient engine. This proprietary technology reduces overnight simulations to a few hours and week-long simulations to a day – while producing identical waveforms at every node.

The table below lists production PLL and DLL circuits for which Analog FastSPICE delivered full SPICE accuracy at least 5X faster.